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LT3750 Capacitor Charger Controller
FEATURES

DESCRIPTIO
Charges Any Size Capacitor Easily Adjustable Output Voltage Drives High Current NMOS FETs Primary-Side Sense--No Output Voltage Divider Necessary Wide Input Range: 3V to 24V Drives Gate to VCC - 2V Available in 10-Lead MS Package
APPLICATIO S

Emergency Warning Beacons Professional Photoflash Systems Security/Inventory Control Systems High Voltage Power Supply Electric Fences Detonators
The LT(R)3750 is a flyback converter designed to rapidly charge large capacitors to a user-adjustable target voltage. A patented boundary mode control scheme* minimizes transition losses and reduces transformer size. The transformer turns ratio and two external resistors easily adjust the output voltage.* A low 78mV current sense accurately limits peak switch current and also helps to maximize efficiency. With a wide input voltage range, the LT3750 can operate from a variety of power sources. A typical application can charge a 100F capacitor to 300V in less than 300ms. The CHARGE pin gives full control of the LT3750 to the user. The DONE pin indicates when the capacitor has reached its programmed value and the part has stopped charging.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents, including 6518733, 6636021.
TYPICAL APPLICATIO
VTRANS 10F
300V, 6A Capacitor Charger
T1 1:10 56F x2 D1 VOUT 300V
* *
+
100F
300 VTRANS = 18V 250 VTRANS = 6V 200 VOUT (V) 150 100
VCC 12V 10F 100k
VCC DONE
VTRANS RVOUT RDCM LT3750 GATE SOURCE
60.4k
43k
OFF ON
CHARGE
M1
GND
RBG 12m 2.49k 100pF
3750 TA01a
50 0 0 0.1 0.2 0.3 TIME (SECONDS) 0.4 0.5
3750 TA03c
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6A Charge Time
VTRANS = 12V
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LT3750
ABSOLUTE
(Note 1)
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RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VTRANS DONE CHARGE VCC GND 1 2 3 4 5 10 9 8 7 6 RBG RVOUT RDCM GATE SOURCE
VCC, VTRANS, GATE, DONE, CHARGE ...................... 24V RBG ....................................................................... 1.5V SOURCE ................................................................... 1V Current into RDCM Pin ........................................ 1mA Current into RVOUT Pin ........................................ 1mA Current into DONE Pin ......................................... 1mA Operating Temperature Range (Note 2) .. - 40C to 85C Storage Temperature Range ................ - 65C to 150C
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/ W
ORDER PART NUMBER LT3750EMS
MS PART MARKING LTBQD
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = VTRANS = 5V unless otherwise specified.
PARAMETER Minimum VCC Minimum VTRANS VCC Quiescent Current VTRANS Quiescent Current CHARGE Pin Current Not Switching, CHARGE = 5V Not Switching, CHARGE = 0V Not Switching, CHARGE = 5V Not Switching, CHARGE = 0V CHARGE = 24V CHARGE = 5V CHARGE = 0V

ELECTRICAL CHARACTERISTICS
CONDITIONS

MIN
TYP 2.8 2.5 1.6 140 24 19 0.87
MAX 3 3 2.5 1 250 1
UNITS V V mA A A A A A A V V s V mV nA mV mV V V A s ns
CHARGE Pin Enable Voltage CHARGE Pin Disable Voltage Minimum CHARGE Pin Low Time VOUT Comparator Trip Voltage VOUT Comparator Overdrive RBG Pin Bias Current DCM Comparator Trip Voltage Current Limit Comparator Trip Voltage DONE Output Signal High DONE Output Signal Low DONE Pin Leakage Current NMOS Minimum On Time GATE Rise Time GATE High Voltage GATE Turn Off Propagation Delay CGATE = 1nF, VCC = 5V CGATE = 1nF, VCC = 24V CGATE = 1nF HighLowHigh Measured RBG Pin 1s Pulse Width, Measured on RBG Pin RBG = 1.2V Measured as VDRAIN - VTRANS, RDCM = 43k (Note 3) 100k to 5V 100k to 5V DONE = 2.5V
1 1.1 20
0.2 1.215
0.6 1.24 30 70 36 78 5 0.1 0.6 50 1.265 500 80 88 0.2 0.2

5 68 4.9
3 22
3.8 22.6 100
4.5 23.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The LT3750E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Refer to Block Diagram for VDRAIN definition.
2
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V V ns
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LT3750 TYPICAL PERFOR A CE CHARACTERISTICS
VCC Pin Current
1.8 225 VTRANS = 24V
CHARGE PIN CURRENT (A)
VTRANS PIN CURRENT (A)
1.7
VCC PIN CURRENT (mA)
VCC = 24V
1.6
VCC = 12V
1.5
VCC = 3V
1.4
1.3 -50 -25
50 25 0 75 TEMPERATURE (C)
CHARGE Pin Enable/Disable Voltage
0.9 0.8 160
CHARGE PIN VOLTAGE (V)
DONE PIN VOLTAGE (mV)
0.7 0.6
CHARGE PIN ENABLE
GATE PIN VOLTAGE (V)
CHARGE PIN DISABLE 0.5 0.4 0.3 0.2 -50
-25
50 25 75 0 TEMPERATURE (C)
60
1.240
CURRENT LIMIT COMPARATOR TRIP VOLTAGE (mV)
DCM Comparator Trip Voltage
DCM COMPARATOR TRIP VOLTAGE (mV) VOUT COMPARATOR TRIP VOLTAGE (V)
RDCM = 43k 50
40
30
20
10 -50
-25
50 25 0 75 TEMPERATURE (C)
UW
100
3750 G01
VTRANS Pin Current
45 40 35 30 25 20 15 10 5 125 100 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 0
CHARGE Pin Current
-50C
200 VTRANS = 12V 175 VTRANS = 3V 150
25C
125C
125
0
4
8
12 16 VCHARGE (V)
20
24
3750 G02
3750 G03
DONE Output Signal Low
25
GATE High Voltage
VCC = 24V
VDONE = 5V RDONE = 100k
20
140
15 VCC = 12V 10
120
100
5
VCC = 5V
100
125
80 -50
-25
75 0 25 50 TEMPERATURE (C)
100
125
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
3750 G04
3750 G05
3750 G06
VOUT Comparator Trip Voltage
Current Limit Comparator Trip Voltage
82
1.236
80
1.232
78
1.228
76
1.224
74
100
125
1.220 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
72 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
3750 G07
3750 G08
3750 G09
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LT3750
PI FU CTIO S
VTRANS (Pin 1): Transformer Supply Pin. Powers the primary coil of the transformer as well as internal circuitry that performs boundary mode detection. Bypass at the pin with a 1F to 10F capacitor. Bypass the primary winding of the transformer with a large capacitor. DONE (Pin 2): Open Collector Indication Pin. When target output voltage is reached, an NPN transistor turns on. Requires a pull-up resistor or current source. Any fault conditions such as thermal shutdown or undervoltage lockout will also turn on the NPN. CHARGE (Pin 3): Charge Pin. Initiates a new charge cycle when brought high or discontinues charging and puts part into shutdown when low. To properly enable the device, a step input with a minimum ramp rate of 1V/s is required. Drive to 1.1V or higher to enable the device; drive below 0.2V to disable the device. VCC (Pin 4): Input Supply Pin. Bypass locally with a ceramic capacitor. A 1F to 10F ceramic capacitor should be sufficient for most applications. GND (Pin 5): Ground Pin. Connect directly to local ground plane. SOURCE (Pin 6): Source Pin. Senses NMOS drain current. Connect NMOS source terminal and current sense resistor to this pin. The current limit is 78mV/RSENSE. GATE (Pin 7): Gate Pin. Connect NMOS gate terminal to this pin. Internal gate driver will drive voltage to within VCC - 2V during each switching cycle. RDCM (Pin 8): Discontinuous Mode Sense Pin. Senses when current in transformer has decayed to zero and initiates a new charge cycle if output voltage target has not been reached. Place a resistor between this pin and the drain of the NMOS. A good choice is a 43k, 5% resistor. RVOUT (Pin 9): Output Voltage VI Converter Pin. Develops a current proportional to output capacitor voltage. Connect a resistor between this pin and the drain of the NMOS. RBG (Pin 10): Output Voltage Sense Pin. Senses the voltage across the RBG resistor, which is proportional to the current flowing into the RVOUT pin. When voltage equals 1.24V, charging is disabled and DONE pin goes low. Connect a resistor (2.5k or less is recommended) from this pin to GND. A 2.49k, 1% resistor is a good choice.
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LT3750
BLOCK DIAGRA
RDONE 2 DONE 2.8V
+ -
VCC UVLO
VCC
VTRANS UVLO 2.5V
+ -
TSD ONE SHOT
VTRANS
DIE TEMP 160C M1 ENABLE QQ SR
+ -
3
CHARGE
ONE SHOT GND 5 10 RBG RBG
W
VTRANS 1 VTRANS T1 1:N D1
*
VOUT RVOUT RVOUT 9
+
COUT
*
DCM COMPARATOR
+ - +-
36mV
RDCM
RDCM 8
VTRANS VDRAIN VCC 4 7 M1
S R Q
GATE
+ +
VOUT COMPARATOR SOURCE 6
-
1.24V
CURRENT LIMIT COMPARATOR
- + -
78mV
RSENSE
3750 BD
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LT3750
OPERATIO
The LT3750 is designed to charge capacitors quickly and efficiently. Operation can be best understood by referring to Figures 1 and 2. Operation proceeds in four phases: 1. Start-up, 2. Primary-side charging, 3. Secondary energy transfer, 4. Discontinuous mode sensing. 1. Start-Up Start-up occurs for approximately 20s after the charge pin is raised high. During this phase, a one-shot enables the master latch and turns on the NMOS. The master latch will remain in the set state until the target output voltage is reached or a fault condition resets it.
1:N ILSEC S2
VTRANS ILPRI
VDRAIN
(1a) Equivalent Circuit During Primary-Side Charging
ILSEC S2
VTRANS ILPRI
VDRAIN
(1b) Equivalent Circuit During Secondary Energy Transfer and Output Detection
1:N ILSEC S2
VDRAIN
VTRANS ILPRI
VDRAIN
(1c) Equivalent Circuit During Discontinuous Mode Detection Figure 1. Equivalent Circuits
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2. Primary Side Charging When the NMOS on latch is set, the gate driver rapidly charges the gate pin to VCC - 2V. The external NMOS turns on forcing VTRANS - VDS(ON) across the primary winding. Consequently, current in the primary coil rises linearly at
ILPRI IPK VTRANS - VDS(ON) LPRI ILSEC
+
VPRI
*
+
IPK N
VOUT + VDIODE LSEC
VSEC
*
+ -
-
S1
-
3750 F01a
VPRI
VTRANS - VDS(ON)
1:N
+
VPRI
*
+
VSEC
-(VOUT + VDIODE) N
VSEC
VOUT + VDIODE
3750 F01b
*
+ -
-
S1
-
-N (VTRANS - VDS(ON))
+
VPRI
*
+
V + VDIODE VTRANS + OUT N VTRANS
VSEC
*
+ -
-
S1
-
3750 F01c
VDS(ON)
VDS(ON)
3750 F02
1. PRIMARY-SIDE CHARGING
3. 2. DISCONTINUOUS SECONDARY MODE ENERGY TRANSFER DETECTION AND OUTPUT DETECTION
Figure 2. Idealized Charging Waveforms
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LT3750
OPERATIO
a rate (VTRANS - VDS(ON))/LPRI. The input voltage is mirrored on the secondary winding -N * (VTRANS - VDS(ON)) which reverse biases the diode and prevents current flow in the secondary winding. Thus, energy is stored in the core of the transformer. 3. Secondary Energy Transfer When current limit is reached, the current limit comparator resets the NMOS on-latch and the device enters the third phase of operation, secondary energy transfer. The energy stored in the transformer core forward biases the diode and current flows into the output capacitor. During this time, the output voltage (neglecting the diode drop) is reflected back to the primary coil. If the target output
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voltage is reached, the VOUT comparator resets the master latch and the DONE pin goes low. Otherwise, the device enters the next phase of operation. 4. Discontinuous Mode Detection Once all the current is transferred to the output capacitor, (VOUT + VDIODE)/N will appear across the primary winding. A transformer with no energy cannot support a DC voltage, so, the voltage across the primary will decay to zero. In other words, the drain of the NMOS will ring down from VTRANS + (VOUT + VDIODE)/N to VTRANS. When the drain voltage falls to VTRANS + 36mV, the DCM comparator sets the NMOS on-latch and a new charge cycle begins. Steps 2-4 continue until the target output voltage is reached.
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LT3750
APPLICATIO S I FOR ATIO
Safety Warning
Large capacitors charged to high voltage can deliver a lethal amount of energy if handled improperly. It is particularly important to observe appropriate safety measures when designing the LT3750 into applications. First, create a discharge circuit that allows the designer to safely discharge the output capacitor. Second, adequately space high voltage nodes from adjacent traces to satisfy printed circuit board voltage breakdown requirements. High voltage nodes are the drain of the NMOS, the secondary side of the transformer, and the output. Transformer Selection The flyback transformer is critical to proper operation of the LT3750. It must be designed carefully so that it does not cause excessive current or voltage on any pin of the part. As with all circuits, the LT3750 has finite bandwidth. In order to give the LT3750 sufficient time to detect the output voltage, observe the following restrictions on the primary inductance:
TIME (s)
LPRI
VOUT * 1s N * IPK
otherwise, the LT3750 may overcharge the output. Linear Technology has worked with several leading magnetic component manufacturers to produce flyback transformers for use with the LT3750. Table 1 summarizes the particular transformer characteristics.
Table 1. Recommended Transformers
MANUFACTURER TDK (www.tdk.com) Sumida (www.sumida.com) Midcom (www.midcom.com) Coilcraft (www.coilcraft.com) PART NUMBER DCT15EFD-U44S003 DCT20EFD-U32S003 C8118 Rev P1 C8117 Rev P1 C8119 Rev P1 32050 32051 32052 DA2032-AL DA2033-AL DA2034-AL SIZE L x W x H (mm) 22.5 x 16.5 x 8.5 30 x 22 x 12 21 x 14 x 8 23 x 18.6 x 10.8 32.3 x 27 x 14 23.1 x 18 x 9.4 28.7 x 22 x 11.4 28.7 x 22 x 11.4 17.2 x 22 x 8.9 17.4 x 24.1 x 10.2 20.6 x 30 x 11.3
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Switching Period The LT3750 employs an open-loop control scheme causing the switching period to decrease with output voltage. Typical switching frequency is between 100kHz to 300kHz. Figure 3 shows typical switching period in an application with a 3A peak current.
20 16 12 8 4 0 0 50 100 150 200 VOUT (V) 250 300
3750 F03
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Figure 3. Typical Switching Period vs VOUT
Output Diode Selection When choosing the rectifying diode, ensure its peak repetitive forward current rating exceeds the peak current (IPK/N) and that the peak repetitive reverse voltage rating exceeds VOUT + (N)(VTRANS). The average current through the diode varies during the charge cycle because the switching period decreases as VOUT increases. The average current through the diode is greatest when the
MAXIMUM IPRI (A) 5 10 3 5 10 3 5 10 3 5 10 LPRI (H) 10 10 10 10 10 10 10 10 10 10 10 TURNS RATIO (PRI:SEC) 1:10 1:10 1:10 1:10 1:10 1:10 1:10 1:10 1:10 1:10 1:10
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APPLICATIO S I FOR ATIO
output capacitor is almost completely charged and is given by:
IAVG,D =
2 VOUT(PK ) + N * VTRANS
(
IPK * VTRANS
)
The output diode's continuous forward current rating must exceed IAVG,D. At a minimum, the diode must satisfy all the previously mentioned specifications to guarantee proper operation. However, to optimize charge time, reverse recovery time and reverse bias leakage current should be considered. Excessive diode reverse recovery times can cause appreciable discharging of the output capacitor thereby increasing charge time. Choose a diode with a reverse recovery time of less than 100ns. Diode leakage current under high reverse bias bleeds the output capacitor of charge, also increasing charge time. Choose a diode that has minimal reverse bias leakage current. Table 2 recommends several output diodes for various output voltages with adequate reverse recovery time.
Table 2. Recommended Output Diodes
PEAK REPETITIVE REVERSE VOLTAGE (V) 400 600 400 1000 400 500
MANUFACTURER Diodes Inc. (www.diodes.com)
PART NUMBER MURS140 MURS160 ES2G US1M BYD147 BYD167
IDC (A) 1 1 2 1 1 1
Philips (www.semiconductors. philips.com)
Bypass Capacitor Selection Use a high quality X5R or X7R dielectric ceramic capacitor placed close to the LT3750 to locally bypass the VCC and VTRANS pins. For most applications, a 1F to 10F ceramic capacitor should suffice for VCC and a 1F to 10F for the VTRANS pin. The high peak currents flowing through the transformer necessitate a larger (>>10F) capacitor to bypass the primary winding of the transformer. Inadequate bypassing
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can result in improper operation. This most often manifests itself in two ways. The first is when the primary winding current looks distorted instead of triangular. This substantially reduces the efficiency and increases the charge time. The second way is when the LT3750 fails to detect discontinuous mode after the first switching cycle. Both of these problems are solved by increasing the amount of capacitive bypassing for the transformer. Choose capacitors that can handle the high RMS ripple currents common in flyback regulators. Output Capacitor Selection For photoflash applications, the output capacitor will be discharged into a Xenon flash bulb. Only a pulse capacitor or photoflash capacitor is able to survive such a harsh event. Igniting a typical Xenon bulb requires approximately 250V to 350V stored on a capacitor on the order of hundreds of microfarads.
Table 3. Recommended Output Capacitor Vendors
VENDOR Rubycon Cornell Dubilier NWL WEBSITE www.rubycon.com www.cornell-dubilier.com www.nwl.com
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NMOS Selection
PACKAGE SMB SMB SMB SMA SOD87 SOD87
Choose an external NMOS with minimal gate charge and on resistance that satisfies current limit and voltage breakdown requirements. The gate is nominally driven to VCC - 2V during each charge cycle. Ensure that this does not exceed the maximum gate to source voltage rating of the NMOS but enhaces the channel enough to minimize the on resistance. Similarly, the maximum drain-source voltage rating of the NMOS must exceed VTRANS + VOUT/N or the magnitude of the leakage inductance spike, whichever is greater. The maximum instantaneous drain current must exceed current limit. Because the switching period decreases with output voltage, the average current through the NMOS is greatest when the output is nearly charged and is given by: IAVG,M =
2 VOUT(PK ) + N * VTRANS
(
IPK * VOUT(PK )
)
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LT3750
APPLICATIO S I FOR ATIO
Table 4. Recommended NMOS Transisitors
MANUFACTURER Philips Semiconductor (www.semiconductors.philips.com) PART NUMBER PHM21NQ15T PHK12NQ10T PHT6NQ10Y PSMN038-100K IRF7488 IRF7493 IRF6644
International Rectifier (www.irf.com)
The transistor's continuous drain current rating must exceed IAVG,M. Table 4 lists recommended NMOS transistors. Setting Current Limit A sense resistor from the SOURCE pin to GND implements current limit. The current limit is nominally 78mV/RSENSE. The average power dissipation rating of the current sense resistor must exceed:
PRESISTOR VOUT(PK ) IPK 2 * RSENSE V 3 OUT(PK ) + N * VTRANS
Additionally, there is approximately a 100ns propagation delay from the time that peak current limit is detected to when the gate transitions to the low state. This delay increases the peak current limit by (VTRANS)(tDELAY)/LPRI. Setting The Target Output Voltage The parameters that determine the target output voltage are the resistors RVOUT and RBG, the turns ratio of the transformer (N), and the voltage drop across the output diode (VDIODE). The target output voltage is set according to the following equation: R VOUT = 1 . 24V * VOUT * N - VDIODE RBG
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ID (A) 22.2 11.6 6.5 6.3 6.3 9.3 10.3 VDS(MAX) (V) 150 100 100 100 80 80 100 VGS(MAX) (V) 20 20 20 20 20 20 20 RDS(ON) (m) 55 28 90 38 29 15 10.7 PACKAGE HVSON8 SO-8 SOT223 SO-8 SO-8 SO-8 DirectFET
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Use at least 1% tolerance resistors for RVOUT and RBG. Choosing large value resistors for RBG decreases the amount of current that charges the parasitic internal capacitances and degrades the response time of the VOUT comparator. This may result in overcharging of the output capacitor. The maximum recommended value for RBG is 2.5k for typical applications. When high primary currents are used, a voltage spike can prematurely trip the output voltage comparator. A 33pF to 100pF capacitor in parallel with RBG is sufficient to filter this spike for most applications. Always check that the voltage waveform on RBG does not overshoot and that it reaches a plateau at maximum VOUT. Discontinuous Mode Detection The RDCM resistor stands off voltage transients on the drain node. A 43k, 5% resistor is recommended for 300V applications. Higher output voltages will require a larger resistor. In order for the LT3750 to properly detect discontinuous mode and start a new charge cycle, the reflected voltage to the primary winding must exceed the discontinuous mode comparator threshold which is nominally 36mV. The worst-case condition occurs when VOUT is shorted to ground. When this occurs, the reflected voltage is simply the diode forward voltage drop divided by N.
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APPLICATIO S I FOR ATIO
Board Layout
The high voltage operation of the the LT3750 demands careful attention to board layout. Observe the following points: 1. Minimize the area of the high voltage end of the secondary winding. 2. Provide sufficient spacing for all high voltage nodes (NMOS drain, VOUT and the secondary winding of the transformer) in order to meet breakdown voltage requirements.
CTRANS VTRANS
PRIMARY
*
SECONDARY
RDONE
1 2
CHARGE VCC
3 4 5 CIN
LT3750
Figure 4. Recommended Board Layout (Not to Scale)
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3. Keep the electrical path formed by C1, the primary of T1 and drain of the NMOS as small as possible. Increasing the size of this path effectively increases the leakage inductance of T1 resulting in an overvoltage condition on the drain of the NMOS.
RBG CPRI T1 1:N DOUT 10 9 8 7 6 RSENSE M1 RDCM RVOUT
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COUT
*
3750 F04
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LT3750
TYPICAL APPLICATIO S
300V, 3A Capacitor Charger
VTRANS C2 10F C3 56F 4, 5 T1 1:10 D1 VOUT 300V
VCC 12V
3A Charging Efficiency
100 VTRANS = 18V 90 EFFICIENCY (%) VTRANS = 12V 80 VTRANS = 6V
VOUT (V)
70
60
50
0
50
100
150 200 VOUT (V)
250
300
3750 TA02b
12
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*
1
+
C4 100F
VCC C1 10F 100k DONE
VTRANS RVOUT RDCM LT3750 GATE SOURCE
60.4k 6, 7 43k
*
10
OFF ON
CHARGE
M1
GND
RBG 25m 2.49k 33pF
3750 TA02a
C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: 330V RUBYCON PHOTOFLASH CAPACITOR D1: DIODES INC. MURS160 M1: PHILIPS PHT6NQ10T T1: TDK DCT15EFD-U44S003 FLYBACK TRANSFORMER
3A Charge Time
300 VTRANS = 18V 250 VTRANS = 6V 200 150 100 50 0 0 0.2 0.4 0.6 TIME (SECONDS) 0.8 1.0
3750 TA02c
Typical Switching Waveforms
NMOS DRAIN CURRENT 1A/DIV
VTRANS = 12V NMOS DRAIN VOLTAGE 20V/DIV 5s/DIV
3750 TA02d
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LT3750
TYPICAL APPLICATIO S
300V, 6A Capacitor Charger
VTRANS C2 10F C3 56F x2 3, 4, 5, 6 T1 1:10 D1 VOUT 300V
VCC 12V
6A Charging Efficiency
100 300
90 EFFICIENCY (%)
VTRANS = 18V VTRANS = 12V VTRANS = 6V VOUT (V)
80
70 100 60 50 0 0 50 100 150 200 VOUT (V) 250 300 0 0.1 0.2 0.3 TIME (SECONDS) 0.4 0.5
3750 TA03c
50
3750 TA03b
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*
1
+
C4 100F
VCC C1 10F 100k DONE
VTRANS RVOUT RDCM LT3750 GATE SOURCE
60.4k 7, 8, 9, 10 43k
*
12
OFF ON
CHARGE
M1
GND
RBG 12m 2.49k 100pF
3750 TA03a
C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: 330V RUBYCON PHOTOFLASH CAPACITOR D1: DIODES INC. MURS160 M1: PHILIPS PHT6NQ10T T1: TDK DCT20EFD-U32S003 FLYBACK TRANSFORMER
6A Charge Time
VTRANS = 18V 250 VTRANS = 6V 200 150 VTRANS = 12V NMOS DRAIN VOLTAGE 20V/DIV NMOS DRAIN CURRENT 2A/DIV
Typical Switching Waveforms
5s/DIV
3750 TA03d
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LT3750
TYPICAL APPLICATIO S
300V, 9A Capacitor Charger
T1 1:10 C2 10F C3 56F x3 3, 4, 5, 6 D1 VTRANS VOUT 300V
VCC 12V
9A Charging Efficiency
100 300
90 EFFICIENCY (%)
VTRANS = 18V VTRANS = 12V
80
VTRANS = 6V
VOUT (V)
70 50 60 0 50 100 150 200 VOUT (V) 250 300 0 0 0.05 0.10 0.15 0.20 TIME (SECONDS) 0.25 0.30
3750 TA04b
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*
1
+
C4 100F
VCC C1 10F 100k DONE
VTRANS RVOUT RDCM LT3750 GATE SOURCE
60.4k 7, 8, 9, 10 43k
*
12
OFF ON
CHARGE
M1
GND
RBG 8m 2.49k 100pF
3750 TA04a
C1: 25V X5R OR X7R CERAMIC CAPACITOR C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: 330V RUBYCON PHOTOFLASH CAPACITOR D1: DIODES INC. MURS160 M1: PHILIPS PHM2INQ15T T1: TDK DCT20EFD-U32S003 FLYBACK TRANSFORMER
9A Charge Time
VTRANS = 18V 250 VTRANS = 6V 200 150 100 VTRANS = 12V NMOS DRAIN VOLTAGE 20V/DIV NMOS DRAIN CURRENT 4A/DIV
Typical Switching Waveforms
5s/DIV
3750 TA04d
3750 TA04c
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LT3750
PACKAGE DESCRIPTIO
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
0.254 (.010) GAUGE PLANE
0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 0.127 0.076 (.005 .003)
MSOP (MS) 0603
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005) 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6 0.497 0.076 (.0196 .003) REF DETAIL "A" 0 - 6 TYP 12345 0.53 0.152 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.86 (.034) REF 4.90 0.152 (.193 .006) 3.00 0.102 (.118 .004) (NOTE 4) 0.50 (.0197) BSC
3750fa
15
LT3750
TYPICAL APPLICATIO U
300V, 9A, 2.5mF Capacitor Charger
VTRANS C2 10F C3 4, 5 56F x3 60.4k 6, 7 T1 1:10 D1 VOUT 300V
*
1
+
C4 2.5mF
VCC 12V
VCC C1 10F 100k DONE
VTRANS RVOUT RDCM LT3750 GATE SOURCE
*
10
43k
OFF ON
CHARGE
M1
GND
RBG 8m 2.49k 100pF
3750 TA05a
C1, C2: 25V X5R OR X7R CERAMIC CAPACITOR C3: 25V SANYO OS-CON 25SVP56M C4: CORNELL DUBILIER 7P252V360N082
D1: DIODES INC. MURS160 M1: PHILIPS PHM21NQ15T T1: MIDCOM 32052 FLYBACK TRANSFORMER
Efficiency
100 95 VTRANS = 18V
Charge Time
300 250 200 VOUT (V) VTRANS = 6V 150 100 50 0 0 1 2 3 4 5 TIME (SECONDS) 6 7 8 VTRANS = 18V VTRANS = 12V
EFFICIENCY (%)
90 VTRANS = 12V 85 VTRANS = 6V 80 75 70
0
50
100
150 200 VOUT (V)
250
300
3750 TA05b
3750 TA05c
RELATED PARTS
PART NUMBER LT3420/LT3420-1 LT3468/LT3468-1 LT3468-2 LT3484-0/LT3484-1 LT3484-2 LT3485-0/LT3485-1 LT3485-2/LT3485-3 DESCRIPTION 1.4A/1A, Photoflash Capacitor Charger with Automatic Top-Off 1.4A, 1A, 0.7A, Photoflash Capacitor Charger 1.4A, 0.7A, 1A Photoflash Capacitor Charger COMMENTS Charges 220F to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, ISD < 1A, 10-Lead MS Package VIN: 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100F, VIN = 3.6V), ISD < 1A, ThinSOT Package VIN: 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100F, VIN = 3.6V), ISD < 1A, 2mm x 3mm 6-Lead DFN Package VIN: 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100F, VIN = 3.6V), ISD < 1A, 3mm x 3mm 10-Lead DFN Driver
1.4A, 0.7A, 1A, 2A Photoflash Capacitor Charger with Output Voltage Monitor and Integrated IGBT
3750fa
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0106 REV A * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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